It is important that data output transitions associated with an integrated circuit, e.g., a memory (dynamic random access memory (DRAM) or static random access memory (SRAM)), or other timing critical device occur in synchronized fashion with a system clock to the integrated circuit. Lack of data output synchronization with the system clock is often described in terms of clock to data latency.
Latency problems have been addressed in the past through use of a delay locked loop (DLL) which is illustrated in the schematic drawing of FIG. 1. In a DLL, phase comparator 2 controls delay line 4 so that the phase difference between clock signals Ckin and Ckout is zero. The time delay provided by delay line 4 stabilizes when the delay between signals Ckin and Ckout is k*T, where T is the period of clock signal Ckin and k is a natural number. Prior art schemes to eliminate clock to data latency generally work with reference to the rising edge of a clock. Latency problems with respect to the falling edge of a clock are not addressed. Consequently, such schemes are not well suited for double data rate applications such as those concerning double data rate synchronous dynamic random access memories (DDR SDRAMs). A need exists to compensate for clock to data latency pertaining to double data rate applications.